Techniques for reducing power consumption in CMP Nuca cache

Current trend of technology scaling makes it possible to put a huge number of transistors on a single die. While dynamic power consumption can benefit from technology scaling, static power consumption get worse, thus making the latter the dominant factor of power consumption in future microprocessors system. As on-chip cache memories require the most part of chip area and number of transistors, techniques have been developed to improve their power efficiency. In this paper, we analyze, in the context of CMP systems, how applications use cache banks depending on their locality, in order to motivate the possibility of applying power-saving techniques to large L2 cache in a CMP environment.